Microsoft Word - camera

نویسندگان

Song jinghui

Wang zongmin

Zhou liang

چکیده

Abstract—A low power 8bit 200MSPS analog-to-digital converter (ADC) is described. The prototype ADC achieves low-power consumption by time-interleaved and stage scaling technique. The pipeline stage and amplifier are designed to guarantee the PVT variation with less current. The ADC is implemented in TSMC 0.35um double-poly-triple-metal CMOS technology and achieved 47.7dB signal-to-noise and distortion (SNDR) at 200MHz with a 41MHz input frequency. The power consumption is 120mW with a 3V supply excluding the output buffer.

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